ICS9DB102 Datasheet, PDF (5/10 Pages) Integrated Circuit Systems – 2 Output PCI Express Buffer with CLKREQ Function

Integrated
Circuit
Systems, Inc.
ICS9DB102
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2Ω, R_P=49.9Ω, Ι_REF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Zo
VHigh
VLow
Vovs
Vuds
V_O = V_x
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
3000
660
-150
-300
Ω
1
850 _mV 1,3
150
1,3
1150 _mV
1,3
1,3
Crossing Voltage (abs) Vcross(abs)
250 350 550 mV 1,3
Crossing Voltage (var) d-Vcross
Variation of crossing over all
edges
12 140 mV 1,3
Long Accuracy
ppm
see Tperiod min-max values
0
ppm 1,2
Average period
Tperiod
100.00MHz nominal
100.00MHz spread
9.9970
9.9970
10.0030 ns
2
10.0533 ns
2
Absolute min period Tabsmin
100.00MHz nominal/spread 9.8720
ns 1,2
Rise Time
t_r
V_OL = 0.175V, V_OH = 0.525V
175
700 ps
1
Fall Time
t_f
V_OH = 0.525V V_OL = 0.175V
175
700 ps
1
Rise Time Variation
d-t_r
30 125 ps
1
Fall Time Variation
d-t_f
30 125 ps
1
Input to Output Delay
t_pd
t_pdbyp
PLL Mode.
Bypass mode
135
185 ps
1
3.2
3.7
ns
1
Duty Cycle
d_t3
Measurement from differential
wavefrom
45
55
%
1
Output-to-Output Skew
t_sk3
V_T = 50%
25
ps
1
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode. Measurement from
differential wavefrom
35
ps
1
t_jcyc-cycbyp
Additve Jitter in Bypass Mode
1_{Guaranteed by design, not 100% tested in production.}
30
ps
1
.
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the}
input clock complies with CK409/CK410 accuracy requirements
3_{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
0852C—09/12/05
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