ICS9DB102 Datasheet, PDF (3/10 Pages) Integrated Circuit Systems – 2 Output PCI Express Buffer with CLKREQ Function

Integrated
Circuit
Systems, Inc.
ICS9DB102
General Description
The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It
attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock
request (OE#) pins make the ICS9DB102 suitable for Express Card applications.
Block Diagram
CLKREQ0#
CLKREQ1#
CLK_INT
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX0
PCIEX1
IREF
Power Groups
Pin Number
VDD
GND
5,9,12,16
6,15
9
6
20
19
20
19
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
0852C—09/12/05
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