ICS9DB102 Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – 2 Output PCI Express Buffer with CLKREQ Function

Integrated
Circuit
Systems, Inc.
Absolute Max
Symbol
Parameter
VDDA
3.3V Core Supply Voltage
VDD
3.3V Output Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
ICS9DB102
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
V_IH
3.3 V +/-5%
2
V_DD + 0.3 V
1
Input Low Voltage
V_IL
3.3 V +/-5%
V_SS - 0.3
0.8
V
1
Input High Current
I_IH
V_IN = V_DD
-5
5
uA
1
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-
up resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up _-200
resistors
uA
1
uA
1
Operating Supply Current
I_DD3.3OP
Full Active, C_L = Full load;
all differential pairs tri-stated
75
100
mA
1
27
50
mA
1
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
99
100
101 MHz 1
7
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
1
4.5
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up to 1st
clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Spread Spectrum Modulation
Frequency
f_MOD
Lexmark Modulation
25
45
KHz
1
PLL Bandwidth
PLL Bandwidth when
BW
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
400
KHz 1
1.2
MHz 1
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage V_OLSMBUS @ I_PULLUP
0.4
V
1
Current sinking at V_OL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
I_PULLUP SMBus SDATA pin
4
T_RI2C (Max VIL - 0.15) to (Min VIH + 0.15)
mA
1
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T_FI2C (Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
0852C—09/12/05
4