ICS9DB102 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – 2 Output PCI Express Buffer with CLKREQ Function

Integrated
Circuit
Systems, Inc.
ICS9DB102
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
2
CLK_INT
3
CLK_INC
4
**CLKREQ0#
5
VDD
6
GND
7
PCIEXT0
8
PCIEXC0
9
VDD
10 SMBDAT
11 SMBCLK
12 VDD
13 PCIEXC1
14 PCIEXT1
15 GND
16 VDD
17 **CLKREQ1#
18 IREF
19 GNDA
20 VDDA
IN
IN
IN
IN
PWR
PWR
OUT
OUT
PWR
I/O
IN
PWR
OUT
OUT
PWR
PWR
IN
OUT
PWR
PWR
3.3V input for selecting PLL Band Width
0 = low, 1= high
"True" reference clock input.
"Complementary" reference clock input.
Output enable for SRC/PCI Express output pair '0'
0 = enabled, 1 = tri-stated
Power supply, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
Power supply, nominal 3.3V
Output enable for SRC/PCI Express output pair '1'
0 = enabled, 1 = tri-stated
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
0852C—09/12/05
2