ICS951403 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – AMD-K7 System Clock Chip

ICS951403
Byte 15: CPU_SDRAM Skew Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
1
0 ^{SDRAM (pdel canned)}
0
Reserved
1
1
CPUC0 & T0 (pdel canned)
1
1
CPUC 1:2 & T 1:2 (pdel canned)
0
Byte 17: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
PCI (3:0) Slew Control
PCI_F Slew Control
CPUCLKC0 Slew Control
CPUCLKT0 Slew Control
Byte 19: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
48MHz Slew Control
24, 48MHz Slew Control
REF0 Slew Control
REF1 Slew Control
SDRAM Slew Control
Notes:
1. PWD = Power on Default
Byte 16: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 18: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
PCI (4:7) Slew Control
AGP1 Slew Control
AGP0 Slew Control
Reserved
Byte 20: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
CPUCLKC1 Slew Control
CPUCLKT1 Slew Control
CPUCLKC2 Slew Control
CPUCLKT2 Slew Control
0486B—02/23/04
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