ICS951403 Datasheet, PDF (4/18 Pages) Integrated Circuit Systems – AMD-K7 System Clock Chip

ICS951403
Byte 1: Output Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
24
37
36
40
39
43
42
46
PWD
DESCRIPTION
1
SEL 24/48
0 = 24MHz 1= 48MHz
1 CPUCLKC0
1 CPUCLKT0
1 CPUCLKC1
1 CPUCLKT1
1 CPUCLKC2
1 CPUCLKT2
1 SDRAM_OUT
Byte 2: PCI Stop Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
7
17
16
14
13
11
10
8
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
PCICLK_F
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 3: CPU Free Running Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
X Reserved
X Reserved
X Reserved
X Reserved
0 Reserved
0 CPU T/C 0
0 CPU T/C 1
0 CPU T/C 2
Byte 4: 24/48MHz Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
7
-
1 Reserved
6
24
1 24-48MHz
5
-
1 48MHz
4
-
1 Reserved
3
-
1 Reserved
2
-
1 Reserved
1
-
0
AGP frequency select
0 = 66.6MHz 1 = 50.0MHz
0
-
1 Reserved
Byte 5: Clock Enable Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
7
-
X Reserved
6
X FS2 Read-back
5
X FS1 Read-back
4
X FS0 Read-back
3
1
1 REF1
2
2
1 REF0
1
20
1 AGP1
0
19
1 AGP0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0486B—02/23/04
Byte 6: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
7
-
0 REF strength 0 = 1X 1 = 2X
6
-
0
0 = CPU C1:2, T1:2 stop
1 = CPU C1:2, T1:2 free running
5
-
0 Reserved
4
-
X SPREAD# read-back
3
-
X CPU_STOP# read-back
2
-
X PCI_STOP# read-back
1
-
X Reserved
0
-
0 AGP speed toggle
Notes:
3. Bytes 7:14 not defined.
4