ICS950818 Datasheet, PDF (5/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950818
BYTE
0
Pin #
Affected Pin
Name
Control Function
Bit 7
-
Spread Enabled
Spread Spectrum Control
Power down mode output level
Bit 6
-
CPUCLKT(1:0)
0= CPU driven in power down
1= undriven
Bit 5
31
3V66_1/VCH_CLK
VCH/66.66 Select
Bit 4
44
CPU_STOP#
Reflects value of pin
Bit 3
30
PCI_STOP#
Reflects value of pin at power up.
Also can be set.
Bit 2
-
-
(Reserved)
Bit 1
46
FS1
Frequency Selection
Bit 0
36
FS0
Frequency Selection
Note: For PCI_STOP# function, refer to table 2.
Type
RW
RW
RW
R
RW
R
R
R
Bit Control
0
1
OFF
ON
x2 IREF Hi-Z
66.66
Stop
Stop
-
-
-
48.00
Active
Active
-
-
-
PWD
0
0
0
X
X
X
X
X
BYTE
1
Pin #
Affected Pin
Name
Control Function
Bit 7
-
-
(Reserved)
CPU_Stop mode output level
Bit 6
-
CPUCLKT(1:0)
0= CPU driven when stopped
1 = undriven
Bit 5 39, 38
CPUCLKT1, CPUCLKC1
(see note)
Allow control of output with
assertion of CPU_STOP#.
Bit 4 43, 42
CPUCLKT0, CPUCLKC0
(see note)
Allow control of output with
assertion of CPU_STOP#.
Bit 3
-
-
(Reserved)
Bit 2 39, 38 CPUCLKT1, CPUCLKC1
Output control
Bit 1 43, 42 CPUCLKT0, CPUCLKC0
Output control
Bit 0
-
-
(Reserved)
Note: CPUCLK(1:0) can be turned on/off by CPU_STOP#. Refer to table 3.
Type
R
Bit Control
0
1
-
-
PWD
X
RW x2 IREF Hi-Z
0
RW
Not
Freerun
Freerun
0
RW
Not
Freerun
Freerun
0
R
-
-
X
RW Disable Enable
1
RW Disable Enable
1
R
-
-
X
BYTE
2
Pin #
Affected Pin
Name
Control Function
Bit 7
47
REF
1X or 0.5X Strength control
Bit 6
14
PCICLK5
Output control
Bit 5
13
PCICLK4
Output control
Bit 4
12
*PCICLK3
Output control
Bit 3
-
-
Reserved
Bit 2
10
*PCICLK2
Output control
Bit 1
9
PCICLK1
Output control
Bit 0
8
PCICLK0
Output control
Note: PCICLK(5:0) can be turned on/off by PCI_STOP#. Refer to table 2.
Type
RW
RW
RW
RW
X
RW
RW
RW
Bit Control
0
1
1X
0.5X
Disable Enable
Disable Enable
Disable Enable
-
-
Disable Enable
Disable Enable
Disable Enable
PWD
0
1
1
1
1
1
1
1
0825F—11/19/03
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