ICS950818 Datasheet, PDF (10/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950818
Table 2
PCI_STOP# SMBus Control Table-Byte 0, Bit 3
PCI_STOP#
(Pin 30)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
0
0
1
0
1
0
0
1
1
1`
Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Table 3
CPUCLKT/C (1:0) Outputs SMBus Control Table
CPU_STOP#
(Pin 45)
0
Byte 1
Bit 4, 5
0
CPUCLKT/C (1:0) Outputs
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 4, and 5.
Table 4
PCICLK_F (2:0) Outputs SMBus Control Table
PCI_STOP#
(Pin 30)
0
Byte 3
Bit 3, 4, 5
0
PCICLK (2:0) Outputs
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Table 5
3V66 (4:2) SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 5
Bit 5
3V66 (4:2)
0
0
0
1
1
0
1
1
Running
Stopped
Running
Running
Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 17, 18, and 19
Table 6
3V66 (1) SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 5
Bit 4
3V66 (1)
0
0
Running
0
1
Stopped
1
0
Running
1
1
Running
Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 31.
0825F—11/19/03
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