ICS950818 Datasheet, PDF (2/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950818
Pin Description
PIN # PIN NAME
1 X1
2 X2
3 GND
4 PCICLK_F0/PCICLK6
5 PCICLK_F1/PCICLK7
6 PCICLK_F2/PCICLK8
7 GND
8 PCICLK0
9 PCICLK1
10 *PCICLK2
11 VDDPCI
12 *PCICLK3
13 PCICLK4
14 PCICLK5
15 VDD3V66
16 GND
17 3V66_2
18 3V66_3
19 3V66_4
20 PCICLK9
21 PD#
22 VDDA
23 GND
24 Vtt_PWRGD#
PIN TYPE
IN
OUT
PWR
OUT
OUT
OUT
PWR
OUT
OUT
OUT
PWR
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
PWR
PWR
IN
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
PCI clock output.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped.
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
0825F—11/19/03
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