ICS950818 Datasheet, PDF (18/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950818
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the
ramping of the power supply until the time that stable clocks are output from the clock chip. If the SMBus Bit 6 of Byte
0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
Rs=33 Ohms
5%
CLK408
Rs=33 Ohms
5%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
TLA
TLB
Rp=49.9 Ohms
1%
CPUCLKT test
point
CPUCLKC test
point
2pF
2pF
5%
5%
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0825F—11/19/03
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