ICS93V850 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS93V850
Preliminary Product Preview
Recommended Operating Condition
T_A = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog/core supply
voltage
V_DD, A_VDD
V_DDI2C
2.3
2.5
2.7
V
2.3
3.6
V
Input voltage level
V_IL
V_IH
-0.3
V_DD-0.4
V
0.4
V_DD+0.3
V
Input differential-pair
DC - CLK_INT, FB_INT
0.36
voltage swing¹
V_ID
AC - CLK_INT, FB_INT
0.5
V_DDQ +0.6
V
V_DDQ +0.6
V
Input differential-pair
crossing voltage
V_IC
0.45x(V_IH-V_IL)
0.55x(V_IH-V_IL) V
Output differential-pair
crossing voltage
V_OC
V
1 _{Differential inputs signal voltages specifies the differential voltage [VTR - VCP] required for switching,}
where VT is the true input level and VCP is the complementary input level.
Timing Requirements
T_A = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Operating clock frequency
freq_op
66
170
Input clock duty cycle
CLK stabilization
d_tin
40
60
from VDD = 3.3V to 1%
T_STAB
target freq.
100
UNITS
MHz
%
µs
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
Jitter; Absoulte Jitter
T_jabs
66MHz
100/125/133/167MHz
120
75
Cycle to Cycle Jitter¹
T_cyc-T_cyc
66MHz
100/125/133/167MHz
110
65
Phase error
t_{(phase error)}
-150
150
Output to Output Skew
T_skew
100
Pulse skew
T_skewp
100
Half Period Jitter
T_jitter H_p 66/100/133/166MHz
-75
75
Typ: Propagation Delay
Time
Bypass Mode CLK to
any output
4
Slew Rate
t_SLEW
Load = 120Ω/14pF
1
1.8
2
Notes:
1. Refers to transition on noninverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t_wH/t_c, were
the cycle (t_c) decreases as the frequency goes up.
UNITS
ps
ps
ps
ps
ps
ps
ps
ps
ns
V/ns
0423H—07/03/03
5