ICS93V850 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

Integrated
Circuit
Systems, Inc.
ICS93V850
Preliminary Product Preview
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 140 MHz
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Slew Rate: 1V/ns - 2V/ns
Pin Configuration
GND
1
CLKC0
2
CLKT0
3
VDD
4
CLKT1
5
CLKC1
6
GND
7
GND
8
CLKC2
9
CLKT2
10
VDD
11
SCLK
12
CLK_INT
13
CLK_INC
14
VDDI²C
15
AVDD
16
AGND
17
GND
18
CLKC3
19
CLKT3
20
VDD
21
CLKT4
22
CLKC4
23
GND
24
48
GND
47
CLKC5
46
CLKT5
45
VDD
44
CLKT6
43
CLKC6
42
GND
41
GND
40
CLKC7
39
CLKT7
38
VDD
37
SDATA
36
FB_INC
35
FB_INT
34
VDD
33
FB_OUTT
32
FB_OUTC
31
GND
30
CLKC8
29
CLKT8
28
VDD
27
CLKT9
26
CLKC9
25
GND
48-Pin TSSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
CLK_INC
PLL
CLK_INT
AVDD
Functionality
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND L
H
LH
L
H Bypassed/Off
GND H
L
HL
H
L Bypassed/Off
2.5V
(nom)
L
H
LH
L
H
On
2.5V
(nom)
H
L
HL
H
L
On
2.5V
(nom)
<20 MHz
<20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Off
0423H—07/03/03
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.