ICS93V850 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS93V850
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLKC(9:0)
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
4, 11, 21, 28,
34, 38, 45,
VDD
12
SCLK
13
CLK_INT
14
CLK_INC
15
VDDI²C
16
AVDD
17
AGND
32
FB_OUTC
33
FB_OUTT
35
FB_INT
36
FB_INC
37
SDATA
TYPE
PWR Ground
DESCRIPTION
OUT "Complementary" clocks of differential pair outputs.
OUT "True" Clock of differential pair outputs.
PWR Power supply 2.5V
IN Clock input of I²C input, 5V tolerant input
IN "True" reference clock input
IN "Complementary" reference clock input
PWR 3.3V power for I²C
PWR Analog power supply, 2.5V
PWR
OUT
OUT
IN
IN
IN
Analog ground.
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Data input for I²C serial input, 5V tolerant input
0423H—07/03/03
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