ICS9250-30 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-30
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table¹
Group
CPU to SDRAM
CPU to 3V66
CPU 66MHz
SDRAM 100MHz
Offset Tolerance
2.5ns 500ps
7.5ns 500ps
CPU 100MHz
SDRAM 100MHz
Offset Tolerance
5.0ns 500ps
5.0ns 500ps
CPU 133MHz
SDRAM 100MHz
Offset Tolerance
0.0ns 500ps
0.0ns 500ps
CPU 133MHz
SDRAM 133MHz
Offset Tolerance
3.75ns 500ps
0.0ns 500ps
SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps
3V66 to PCI
PCI to PCI
USB & DOT
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = 0 pF; Select @ 66M
2
V_SS-0.3
-5
-5
-200
I_DD3.3PD C_L = 0 pF; With input address to Vdd or GND
V_DD+0.3 V
0.8
V
5
µA
µA
µA
100 mA
600 µA
Input frequency
F_i
V_DD = 3.3 V;
Pin Inductance
Input Capacitance¹
L_pin
C_IN Logic Inputs
C_out Out put pin capacitance
Transition Time¹
Settling Time¹
Clk Stabilization¹
C_INX
T_trans
T_s
T_STAB
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From V_DD = 3.3 V to 1% target Freq.
Delay
t_PZH,t_PZH output enable delay (all outputs)
t_PLZ,t_PZH output disable delay (all outputs)
1_{Guarenteed by design, not 100% tested in production.}
14.318
7
5
6
27
45
3
3
3
1
10
1
10
MHz
nH
pF
pF
pF
mS
mS
mS
nS
nS
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