ICS9250-30 Datasheet, PDF (3/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-30
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Description
PWD
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 _{CPUCLK SDRAM}
FS4 FS3 FS2 FS1 FS0 ^MHz
MHz
0000 0
66.67
100.00
0 0 0 0 1 60.00
90.00
0001 0
66.80
100.20
0001 1
68.33
102.50
00 10 0
70.00
105.00
0 0 1 0 1 75.00
112.50
00 11 0
80.00
120.00
00 11 1
83.00
124.50
0 1 0 0 0 100.00 100.00
0 1 0 0 1 90.00
90.00
0 1 0 1 0 100.30 100.30
0 1 0 1 1 103.00 103.00
0 1 1 0 0 105.00 105.00
0 1 1 0 1 110.00 110.00
Bit
(2, 7:4)
0
0
1
1
1
1
1
1
0
1
115.00
200.00
115.00
200.00
1 0 0 0 0 133.33 133.33
1 0 0 0 1 166.67 166.67
1 0 0 1 0 133.70 133.70
1 0 0 1 1 137.00 137.00
1 0 1 0 0 140.00 140.00
1 0 1 0 1 145.00 145.00
1 0 1 1 0 150.00 150.00
1 0 1 1 1 160.00 160.00
1 1 0 0 0 133.33 100.00
1 1 0 0 1 166.67 125.00
1 1 0 1 0 133.70 100.28
1 1 0 1 1 137.00 102.75
1 1 1 0 0 140.00 105.00
1 1 1 0 1 145.00 108.75
1 1 1 1 0 150.00 112.50
1 1 1 1 1 160.00 120.00
Bit 3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
Bit 1
0- Normal
1- Spread spectrum enable
Bit 0
0- Running
1- Tristate all outputs
3V66
MHz
PCICLK
IOAPIC
MHz
Spread Precentage
66.67
60.00
66.80
68.33
70.00
75.00
80.00
83.00
66.67
60.00
66.87
68.67
70.00
73.33
76.67
66.67
66.67
83.34
66.85
68.50
70.00
72.50
75.00
80.00
66.67
83.34
66.85
68.50
70.00
72.50
75.00
80.00
33.33
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.33
30.00
33.43
34.33
35.00
36.67
38.33
33.33
33.33
41.67
33.43
34.25
35.00
36.25
37.50
40.00
33.33
41.67
33.43
34.25
35.00
36.25
37.50
40.00
16.67
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.67
15.00
16.72
17.17
17.50
18.33
19.17
16.67
16.67
20.83
16.71
17.13
17.50
18.13
18.75
20.00
16.67
20.83
16.71
17.13
17.50
18.13
18.75
20.00
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00001
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. The I²C readback for Bit 2, 7:4 indicate the revision code.
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3