ICS9250-30 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-30
Preliminary Product Preview
General Description
The ICS9250-30 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-30 employs a proprietary
closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I²C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN
NUMBER
PIN NAME
1, 9, 10, 18, 25,
32, 33, 37, 45
VDD
2
X1
3
4, 5, 14, 21,
28, 29, 36,
41, 49
8, 7, 6
11
12
20, 19, 17,
16, 15
13
X2
GND
3V66 [2:0]
PCICLK0
FS0
PCICLK1
FS1
PCICLK [7:3]
PCICLK2
SEL24_48#
22
PD#
23
SCLK
24
SDATA
48MHz
34
FS3
35
38
48, 47, 44, 43,
42, 40, 39, 31,
30, 30, 27, 26
50
FS2
24_48MHz
SDRAM_F
SDRAM [11:0]
GNDL
51, 52
CPUCLK [1:0]
53, 55
54
56
VDDL
IOAPIC
FS4
REF0
TYPE
DESCRIPTION
PWR
IN
OUT
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
IN
IN
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock outputs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock outputs.
Logic input frequency select bit. Input latched at power on.
OUT 3.3V PCI clock outputs.
OUT 3.3V PCI clock output.
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
Input logic select. When logic "0" is selected pin 35 = 48MHz
When logic "1" is selected pin 35 = 24MHz.
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
Clock input of I²C input.
Data input for I²C serial input.
3.3V Fixed 48MHz clock output for USB.
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
3.3V 24 or 48MHz output.
3.3V free running 100MHz SDRAM not affected by I²C
OUT
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I²C.
PWR
OUT
PWR
OUT
IN
OUT
Ground for 2.5V power supply for CPU & APIC.
2.5V Host bus clock output. Output frequency derived from FS pins.
2.5V power suypply for CPU, IOAPIC.
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
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