ICS9250-30 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-30
Preliminary Product Preview
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-
X
-
X
-
X
35
0
-
1
34
1
-
1
38
1
Description
FS3#
FS0#
FS2#
24_48MHz #
(Reserved)
48MHz
(Reserved)
SDRAM_F
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
20
1
19
1
17
1
16
1
15
1
13
1
12
1
11
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
39
1
40
1
42
1
43
1
44
1
46
1
47
1
48
1
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
8
1
6
1
7
1
-
X
54
1
-
X
51
1
52
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Description
3V66_2
3V66_0
3V66_1
FS4#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Byte 5: Control Register
(1 = enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-
1
-
1
-
1
-
1
26
1
27
1
30
1
31
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit Pin# PWD
Description
Bit7
-
0 Reserved (Note)
Bit6
-
0 Reserved (Note)
Bit5
-
0 Reserved (Note)
Bit4
-
0 Reserved (Note)
Bit3
-
0 Reserved (Note)
Bit2
-
1 Reserved (Note)
Bit1
-
1 Reserved (Note)
Bit0
-
0 Reserved (Note)
Note: Don’t write into this register, writing into this register
can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Third party brands and names are the property of their respective owners.
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