ICS9248-192 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for Transmeta Systems

ICS9248-192
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
2,7:4
Bit3
Bit1
Bit0
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
CPU
60
60
60
60
66.6
66.6
66.6
66.6
67.32
68.64
69.96
72.6
61.5
63
64
65
60
PCI
30
30
30
30
33.3
33.3
33.3
33.3
33.66
34.32
34.98
36.3
30.75
31.5
32
32.5
30
Spread %
-0.4 % down spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
-0.4 % down spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
2% over-clocking
4% over-clocking
6% over-clocking
10% over-clocking
over-clocking
over-clocking
over-clocking
over-clocking
+/- 0.5% center spread
10 00
1
66.6
33.3
+/- 0.5% center spread
1
0
0
1
0
50
25
1
0
0
1
1
48
24
10 10
0
58.8
29.4
10 10
1
57.6
28.8
10 11
0
56.4
28.2
1
0
1
1
1
54
27
under-clocking
under-clocking
2% under-clock
4% under-clock
6% under-clock
10% under-clock
1
1
0
0
0
60
30
-1.4 % down spread
1
1
0
0
1
60
1
1
0
1
0
60
1
1
0
1
1
60
30
-1.6 % down spread
30
-1.8 % down spread
30
-2.0 % down spread
11 10
0
66.6
33.3
-1.4 % down spread
11 10
1
66.6
33.3
-1.6 % down spread
11 11
0
66.6
33.3
-1.8 % down spread
11 11
1
66.6
33.3
-2.0 % down spread
Hardware latch inputs can only access these frequencies
0-Frequency is seleced by hardware select. Latched input
1-Frequency is seleced by Bit 2, 7:4
0-Normal 1-Spread spectrun Enabled
0-Running 1-Tristate all outputs
Note: PWD = Power-Up Default
PWD
00000
0
0
0
0540E—08/20/03
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