ICS9248-192 Datasheet, PDF (3/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for Transmeta Systems

ICS9248-192
CPU Select Functions
SEL 66/60#
0
1
CPU (MHz)
60MHz
66.6MHz
Power Management
Clock Enable Configuration
CPU_STOP#
X
0
0
1
1
PCI_STOP#
X
0
1
0
1
PWR_DWN#
0
1
1
1
1
CPUCLK
Low
Low
Low
60/66.6MHz
60/66.6MHz
PCICLK REF
Low Stopped
Low Running
33.3 MHz Running
Low Running
33.3 MHz Running
Crystal
Off
Running
Running
Running
Running
VCOs
Off
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of
the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock
network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-192 Power Management Requirements
SIGNAL
CPU_ STOP#
PCI_STOP#
PD#
SIGNAL STATE
0 (Disabled)²
1 (Enabled)¹
0 (Disabled)²
1 (Enabled)¹
1 (Normal Operation)³
0 (Power Down)⁴
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
0540E—08/20/03
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