ICS9248-146 Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-146
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 2,3 0 REF strength 0=1X, 1=2X
Bit6 45
CPUCLK2 - Stop - Control
0 0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit5 -
X AGPSEL (Readback)
Bit4 -
X MODE (Readback)
Bit3 -
X CPU_STOP# (Readback)
Bit2 -
X PCI_STOP# (Readback)
Bit1 -
X SDRAM_STOP# (Readback)
Bit0 -
AGP Speed Toggle
0 0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
1 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
1 Reserved
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