ICS9248-146 Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-146
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
47
46
45
-
PWD
DESCRIPTION
1
Sel24_48
(1:24MHz, 0:48MHz)
1 Reserved
1 Reserved
1 Reserved
1 CPUCLK0
1 CPUCLK1
1 CPUCLK2
1 Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
13
12
11
10
9
8
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
1 PCICLK_F
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
33
34
36
37
38
40
41
42
PWD
DESCRIPTION
1 SDRAM7
1 SDRAM6
1 SDRAM5
1 SDRAM4
1 SDRAM3
1 SDRAM2
1 SDRAM1
1 SDRAM0
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
21
20
26
27
28
30
31
PWD
DESCRIPTION
1 Reserved
1 24_48MHz
1 48MHz
1 SDRAM12
1 SDRAM11
1 SDRAM10
1 SDRAM9
1 SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
2
3
17
16
PWD
DESCRIPTION
X FS3 (Readback)
X FS2 (Readback)
X FS1 (Readback)
X FS0 (Readback)
1 REF1
1 REF0
1 AGPCLK1
1 AGPCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
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