ICS581-01 Datasheet, PDF (5/6 Pages) Integrated Circuit Systems – Zero-Delay Glitch-Free Clock Multiplexer

ICS581-01, -02
Zero-Delay Glitch-Free Clock Multiplexer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
ICS581G-01I
-40
85
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH
INA and INB only
(VDD/2)+1 VDD/2
V
Input Low Voltage, VIL
INA and INB only
VDD/2 (VDD/2)-1 V
Input High Voltage, VIH
Non-clock inputs
2
V
Input Low Voltage, VIL
Non-clock inputs
0.8
V
Output High Voltage, VOH
IOH=-12mA
VDD-0.5
V
Output Low Voltage, VOL
IOL=12mA
0.5
V
Operating Supply Current, IDD
100 MHz inputs, no Load
26
mA
Short Circuit Current
±70
mA
On-chip pull-up resistor
250
kΩ
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
4
pF
Input Frequency
Note 6
6
200
MHz
Input Clock Duty Cycle
at VDD/2
30
70
%
Skew, selected input clock to FBIN
Note 1
-250
0
250
ps
Skew, between any output clocks
Note 2
-250
0
250
ps
Transition Detector Timeout, DIV=0
ICS581-02 only
2
3
4
INB periods
Transition Detector Timeout, DIV=1
ICS581-02 only
32
48
64
INB periods
Frequency Transition Time, 50 to 150 MHz Note 3, 4
70
200
µs
Frequency Transition Time, 100 to 100 MHz Note 3, 5
4
10
µs
Output Clock Rise Time
0.8 V to 2 V
1
2
ns
Output Clock Fall Time
2 V to 0.8 V
1
2
ns
Output Clock Duty Cycle, less than 133 MHz at VDD/2, no load
45
55
%
Output Clock Duty Cycle, greater than 133 MHz at VDD/2, no load
40
60
%
Output Clock Duty Cycle with S0=S1=1
at VDD/2, no load
40
60
%
Absolute Output Clock Period Jitter
Deviation from mean
±150
ps
One Sigma Output Clock Period Jitter
40
ps
Note 1. Assumes clocks with same rise times, measured at VDD/2.
Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2.
The maximum skew between any 2 clocks is 250 ps not 500 ps.
Note 3. Time taken for output to lock to new clock when mux selection changed from INA to INB.
Note 4 With 50 MHz on INA and 150 MHz on INB.
Note 5. With 100 MHz on both INA and INB, 180° out of phase.
Note 6. For correct operation, FBIN requires a rail to rail clock. At high frequencies, this may mean that the ICS581 output driving
FBIN cannot drive other loads.
MDS 581-01, 581-02 A
5
Revision 041100
Printed 11/14/00
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