ICS950910 Datasheet, PDF (4/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950910
Pin Description (Continued)
PIN PIN
# NAME
29 DDRC5
30 DDRT5
31 DDRC4
32 DDRT4
33 GND
34 VDD2.5
35 DDRC3
36 DDRT3
37 DDRC2
38 DDRT2
39 GND
40 VDD2.5
41 DDRC1
42 DDRT1
43 DDRC0
44 DDRT0
45 BUF_IN
46 FBOUT
47 GND
48 CPUT_CS
49 CPUC_CS
50 VDDCPU2.5
51 VDDCPU3.3
52 CPUCLKC/CPUCLKODC
53 CPUCLKT/CPUCLKODT
54 GND
55 VDDREF
56 Vtt_PWRGD#**/REF1
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
IN
DESCRIPTION
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
True clock of differential pair 2.5V push-pull CPU outputs.
Complimentary" clocks of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
0735A—03/18/04
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