ICS950910 Datasheet, PDF (12/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950910
Byte 20: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCICLK_F
Group Skew
Control
Reserved
PWD
1
0
0
0
1
0
0
0
Description
These 4 bits can change the CPU to PCIF skew from 1.4ns -
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
Reserved
Byte 21: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUCLKT/C_CS
Slew Rate Control
CPUCLKT1/C1
Slew Rate Control
CPUCLKT2/C2
Slew Rate Control
AGP_0
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
CPUCLKT/C_CS clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
CPUCLKT1/C1 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
CPUCLKT2/C2 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
AGP_0 clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 22: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP(2:1)
Slew Rate Control
PCICLK_F
Slew Rate Control
PCICLK(7:4)
Slew Rate Control
PCICLK(3:0)
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
AGP(2:1) clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
PCICLK_F clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(7:4) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(3:0) clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 23: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
REF
Slew Rate Control
IOAPIC(1:0)
Slew Rate Control
48MHz
Slew Rate Control
24_48MHz
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
REF clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
IOAPIC(1:0) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
48MHz clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
24_48MHz clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
0735A—03/18/04
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