ICS950910 Datasheet, PDF (11/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950910
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_INV
Reserved
CPU_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
Description
0 AGP Phase Inversion bit
0 Reserved
0 CPU T/C Phase Inversion bit
0 CPUT/C_CS Phase Inversion bit
1
0
0
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
1
Table 1
Div (3:2)
00 01 10 11
Div (1:0)
00
/2
/4
/8 /16
01
/3
/6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/4
/8 /16 /32
01
/3
/6 /12 /24
10
/5 /10 /20 /40
11
/9 /18 /36 /72
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUCLKT/C_CS
Group Skew
Control
CPUCLKT/C
Group Skew
Control
AGPCLK
Group Skew
Control
Reserved
Reserved
PWD
1
0
1
0
1
0
X
X
Description
These 2 bits delay the CPUCLKT/C_CS with respect to
CPUCLKT/C
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
These 2 bits delay the CPUCLKT/C clock with respect to
CPUCLKT/C_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
These 2 bits delay the AGPCLK clocks with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
PCICLK(5:0)
Group Skew
Control
PWD
1
0
0
0
1
0
0
0
Description
Reserved
These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns -
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
0735A—03/18/04
11