ICS950910 Datasheet, PDF (19/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950910
Power Down Waveforms
0ns
25ns
50ns
1
2
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
PD#
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Group Offset Waveforms
0ns
10ns
20ns
30ns
40ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
Cycl e R epeat s
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Skews at Common Transition Edges
GROUP
SYMBOL
CONDITIONS
CPU408 to CPUCS
CPU
50% to 1.25V
CPU Open Drain to CPUCS
CPU
50% to 1.25V
CPUCS to PCI
S_CPU-PCI
1.25 to 1.5V
CPU408 to PCI
S_CPU-PCI
1.25 to 1.5V
AGP to PCI
S_AGP-PCI
1.5 to 1.5V
1_{Guaranteed by design, not 100% tested in production.}
0735A—03/18/04
19
MIN TYP MAX UNITS
0
250
ps
0
75 250
0
2.8
4
ns
0
3.8
4
ns
1.5 2.87 3.5
ns