ICS9248-189 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

ICS9248-189
Advance Information
Byte 0: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 38
0
CLK_STOP#
(1 = PD#, 0 = CLK_STOP#)
Bit 6
4
0 FS2
Bit 5
5
0 FS1
Bit 4 22
0 FS0
Bit 3
-
0
Hardware / Software Frequency
selection
Bit 2
-
1 Reserved
Bit 1 46
0 FS3
Bit 0
-
0 Reserved
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
0 Reserved
Bit 6
-
0 Reserved
Bit 5
-
0 Reserved
Bit 4
-
0 Reserved
Bit 3 40, 41
1
CPUCLKC0/T0
( 1 = 1X, 0 = 1.5X )
Bit 2 42
1 CPUCLK_CS
Bit 1 41
1 CPUCLKT0
Bit 0 40
1 CPUCLKC0
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 15
1 PCICLK6
Bit 6 12
1 PCICLK5
Bit 5 11
1 PCICLK4
Bit 4 10
1 PCICLK3
Bit 3 9
Bit 2 8
1 PCICLK2
1 PCICLK1
Bit 1 5
Bit 0 4
1 PCICLK0
1 PCICLK_F
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
0 Reserved
Bit 6 23
0 SEL24_48#
Bit 5 22
1 48MHz
Bit 4 23
1 24_48MHz
Bit 3 27
Bit 2 28, 29
1 SDRAM_F
1 SDRAM(5:4)
Bit 1 32, 33
Bit 0 36, 37
1 SDRAM(3:2)
1 SDRAM(1:0)
Byte 4: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
0 Reserved
Bit 6 -
0 Reserved
Bit 5 -
0 Reserved
Bit 4 -
0 Reserved
Bit 3 -
0 Reserved
Bit 2 -
0 Reserved
Bit 1 -
0 Reserved
Bit 0 -
0 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
22
X FS0 (readback)
5
X FS1 (readback)
4
X FS2 (readback)
46
X FS3 (readback)
23
X SEL24_48# (readback)
46
1 REF2
47
1 REF1
48
1 REF0
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