ICS9248-189 Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

Integrated
Circuit
Systems, Inc.
ICS9248-189
Advance Information
AMD - K7™ Clock Generator for Mobile System
Recommended Application:
VIA K7/KN/KX-133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 7 - SDRAM @ 3.3V
• 8 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
• Support power management via I²C programing
• Spread spectrum for EMI control
(± 0.25% to ± 0.06% center, or 0 to -0.5% or -1.0% down
spread)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU - CPU Skew: <175ps
• CPU - SDRAM Skew: ±125ps
• CPU - PCI Skew: ±100ps
• PCI - PCI Skew: <500ps
Pin Configuration
VDDREF
1
X1
2
X2
3
*FS2/PCICLK_F
4
*FS1/PCICLK0
5
VDDPCI
6
GND
7
PCICLK1
8
PCICLK2
9
PCICLK3
10
PCICLK4
11
PCICLK5
12
GND
13
VDDPCI
14
PCICLK6
15
*SDRAM_STOP#
16
*PCI_STOP#
17
BUFFER_IN
18
AVDD
19
GND
20
GND
21
*FS0/48MHZ
22
*SEL24_48#/24_48MHz
23
VDD48
24
48
REF0¹
47
REF1
46
REF2/FS3*
45
GND
44
GND
43
VDD
42
CPUCLK_CS
41
CPUCLKT0²
40
CPUCLKC0²
39
CPU_STOP#*
38
CLK_STOP#*/PD#
37
SDRAM0
36
SDRAM1
35
VDDSDR
34
GND
33
SDRAM2
32
SDRAM3
31
GND
30
VDDSDR
29
SDRAM4
28
SDRAM5
27
SDRAM_F
26
SCLK
25
SDATA
48-Pin 300mil SSOP & 240mil TSSOP
* Internal Pull-up Resistor of 120K to VDD
1 _{These outputs have double strength to drive 2 loads.}
2 _{These outputs can be set to 1X or 1.5X strength}
through I²C
Block Diagram
PLL2
X1
X2
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
CLK_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
PCI
DIVDER
Stop
SDRAM
DIVIDER
Stop
Functionality
48MHz
24_48MHz
REF (2:0)
3
CPUCLK_CS
CPUCLKT0
CPUCLKC0
PCICLK (6:0)
7
PCICLK_F
SDRAM (5:0)
6
SDRAM_F
FS2 FS1 FS0 CPU PCI Spread Percentage
0
0
0 100.00 33.33 +/- 0.35% Center Spread
0
0
1 133.33 33.33 +/- 0.35% Center Spread
0
1
0 100.00 33.33 0 to - 0.5% Down Spread
0
1
1 133.33 33.33 0 to - 0.5% Down Spread
1
0
0 100.00 33.33 +/- 0.6% Center Spread
1
0
1 133.33 33.33 +/- 0.6% Center Spread
1
1
0 100.00 33.33
No Spread
1
1
1 133.33 33.33
No Spread
Note: For a complete functionality table please see table in
page 3.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
9248-189 Rev - 08/10/01
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ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.