ICS9248-189 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

ICS9248-189
Advance Information
General Description
The ICS9248-189 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-189 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I²C interface allows changing functions, stop clock programming and frequency selection.
Pin Descriptions
PIN NUMBER
1, 6, 14, 24,
30, 35, 43
2
PIN NAME
VDD
X1
3
X2
FS2^{1, 2}
4
PCICLK_F
5
7, 13, 21, 31, 34, 44, 45
15, 12, 11, 10, 9, 8
FS1^{1, 2}
PCICLK0
GND
PCICLK (6:1)
16
SDRAM_STOP#¹
17
PCICLK_STOP#¹
18
BUFFER IN
19
AVDD
20
AGND
FS0^{1, 2}
22
48MHz
SEL24_48#^{1, 2}
23
24_48MHz
25
SDATA
26
SCLK
27
SDRAM_F
28, 29, 32, 33, 36, 37 SDRAM (5:0)
CLK_STOP#¹
38
PD#
TYPE
PWR
IN
OUT
IN
OUT
IN
OUT
PWR
OUT
IN
IN
IN
PWR
PWR
IN
OUT
IN
OUT
I/O
IN
OUT
OUT
IN
IN
DESCRIPTION
Power supply, nominal 3.3V
Crystal input, has internal load cap (36pF) and feedback
resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF).
Frequency select pin, latched input
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin, latched input
PCI clock output
Ground
PCI clock outputs
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level,
when input low.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low.
Input to Fanout Buffers for SDRAM outputs.
Supply for core, & CPU 3.3V
Analog ground
Frequency select pin, latched input
48MHz output clock
Logic input to select 24 or 48MHz
24MHz/48MHz clock output
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
Free running SDRAM clock not affected by SDRAM_STOP# for
power management.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Powers down chip, active low except XTAL and CPUCLK_T0
& CPUCLKC0.
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the VCO
and the crystal are stopped. The latency of the power down will not
be greater than 3ms.
39
40
41
42
46
47, 48
CPU_STOP#^1,
CPUCLKC0
CPUCLKT0
CPUCLK_CS
REF2
FS3^{1, 2}
REF0 (1:0)
IN
OUT
OUT
OUT
OUT
IN
OUT
Only stops CPUCLK_CS
"Complementary" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
CPU clock to the chipset
14.318 Mhz reference clock
Frequency select pin, latched Input
14.318 Mhz reference clock
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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