ICS9248-189 Datasheet, PDF (12/15 Pages) Integrated Circuit Systems – AMD - K7™ Clock Generator for Mobile System

ICS9248-189
Advance Information
CLK_STOP# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
CLK_STOP# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to
powering down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When CLK_STOP# is active low all clocks need to be
driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The
power down latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP#
is considered to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
CLK_STOP#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-189 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. CLK_STOP# is an input pin which stops all clocks, expcpt XTAL and CPUCLKT0/CPUCLKC0
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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