ICS84314-02 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD
H
X
L
L
L
↑
M
X
Data
Data
Inputs
S_LOAD
X
X
L
L
H
X
L
L
H
X
↑
L
H
X
↓
L
H
X
L
L
H
X
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces outputs LOW.
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32 16
8
M5 M4 M3
4
M2
2
1
M1 M0
250
125
0
0
1
1
1
1
1
0
1
252
126
0
0
1
1
1
1
1
1
0
254
127
0
0
1
1
1
1
1
1
1
256
128
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
348
1
0
1
0
1
1
1
0
0
698
349
1
0
1
0
1
1
1
0
1
700
350
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input
frequency of 16MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
N1 Logic
0
0
1
1
Input
N0 Logic
0
1
0
1
N Divide
1
2
4
8
Output Frequency (MHz)
Q0:Q3, nQ0:nQ3
Minimum Maximum
250
700
125
350
62.5
175
31.25
87.5
84314AY-02
www.icst.com/products/hiperclocks.html
4
REV. B NOVEMBER 17, 2005