ICS84314-02 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5
29, 30, 31
3, 4, 32
M4, M5, M8,
M0, M1, M2
M6, M7, M3
Input Pulldown _{M divider inputs. Data latched on LOW-to-HIGH transition}
Input Pullup ^{of nP_LOAD input. LVCMOS / LVTTL interface levels.}
6
7
8, 17
9, 10
V_EE
V_CC
V_CCO
Q0, nQ0
Power
Power
Power
Output
Negative supply pin.
Core power supply pin.
Output supply pins.
Differential output for the synthesizer. LVPECL interface levels.
11, 12
Q1, nQ1 Output
Differential output for the synthesizer. LVPECL interface levels.
13, 14
Q2, nQ2
Output
Differential output for the synthesizer. LVPECL interface levels.
15, 16
Q3, nQ3
Output
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inverted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
19
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
20
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
21
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
22
V_CCA
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
23
XTAL_SEL
Input Pullup reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
24
TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
25, 26
27
28
XTAL_IN,
XTAL_OUT
nP_LOAD
VCO_SEL
Input
Input
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Pulldown
Parallel load input. Determines when data present at M8:M0
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84314AY-02
www.icst.com/products/hiperclocks.html
3
REV. B NOVEMBER 17, 2005