ICS84314-02 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes nP_LOAD input is initially LOW. The data on inputs M0 through
operation using a 16MHz crystal. Valid PLL loop divider M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
values for different crystal or input frequencies are defined sition of the nP_LOAD input, the data is latched and the M divider
in the Input Frequency Characteristics, Table 5, NOTE 1. remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
The ICS84314-02 features a fully integrated PLL and there- set the M divider to a specific default state that will automatically
fore requires no external components for setting the loop occur during power-up. In parallel mode, the N output divider is
bandwidth. A parallel-resonant, fundamental crystal is used set to 2. In serial mode, the N output divider can be set for either
as the input to the on-chip oscillator. The output of the os- ÷1, ÷2, ÷4 or ÷8. The relationship between the VCO frequency,
cillator is divided by 16 prior to the phase detector. With a the crystal frequency and the M divider is defined as follows:
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
fVCO
=
fxtal
16
x 2M
700MHz. The output of the M divider is also applied to the The M value and the required values of M0 through M8 are shown
phase detector.
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz refer-
The phase detector and the M divider force the VCO output ence are defined as 125 ≤ M ≤ 350. The frequency out
frequency to be 2M times the reference frequency by ad- is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1
justing the VCO control voltage. Note that for some values
N 16
N
of M (either too high or too low), the PLL will not achieve Serial operation occurs when nP_LOAD is HIGH and S_LOAD
lock. The output of the VCO is scaled by a divider prior to is LOW. The shift register is loaded by sampling the S_DATA bits
being sent to each of the LVPECL output buffers.The divider with the rising edge of S_CLOCK. The contents of the shift regis-
provides a 50% output duty cycle.
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
The programmable features of the ICS84314-02 support put divide values are latched on the HIGH-to-LOW transition of
two input modes to program the M divider. The two input S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
operational modes are parallel and serial. Figure 1 shows passed directly to the M divider and N output divider on each
the timing diagram for each mode. In parallel mode, the rising edge of S_CLOCK.
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
*NULL *NULL SSC0 **N1 **N0 M8
tt
SH
M7 M6 M5 M4 M3 M2 M1 M0
nP_LOAD
M0:M8
t
S
PARALLEL LOADING
M, N
nP_LOAD
tt
SH
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
TABLE 1A. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
TABLE 1B. SSC FUNCTION TABLE
N1 Logic Value N0 Logic Value N Output Divide
SSC0
SSC State
0
0
÷1
0
Off (Power-up Default)
0
1
÷2 (Power-up Default)
1
0
÷4
1
1
÷8
1
TBD
*NOTE: The NULL timing slot must be observed.
**NOTE: “N” can only be controlled through serial loading.
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
2