ICS84314-02 Datasheet, PDF (10/17 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
CRYSTAL INPUT INTERFACE
The ICS84314-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF paral-
lel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
X1
18pF Parallel Cry stal
XTAL_IN
C1
22p
XTAL_OUT
C2
22p
ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different lay-
outs which are recommended only as guidelines. Other suit-
able clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
84314AY-02
www.icst.com/products/hiperclocks.html
10
REV. B NOVEMBER 17, 2005