ICS840004-01 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840004-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
f_OUT
tsk(o)
Output Frequency Range
Output Skew; NOTE 1, 3
56
TBD
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.52
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz @ Integration Range:
1.875MHz - 20MHz
0.65
62.5MHz @ Integration Range:
1.875MHz - 20MHz
0.55
t_L
t_R / t_F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
400
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
175
Units
MHz
ps
ps
ps
ps
ms
ps
%
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
f
OUT
tsk(o)
Output Frequency Range
Output Skew; NOTE 1, 3
56
TBD
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.48
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz @ Integration Range:
1.875MHz - 20MHz
0.59
62.5MHz @ Integration Range:
1.875MHz - 20MHz
0.53
t_L
t /t
RF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
450
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
175
Units
MHz
ps
ps
ps
ps
ms
ps
%
8400042AG-01
www.icst.com/products/hiperclocks.html
4
REV. B JANUARY 3, 2006