ICS840004-01 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840004-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
F_SEL0
Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
2, 9
3
4
5
6
7
8
10
11,
12
13, 19
14, 15
17, 18
16
20
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V_DDA
V_DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
V_DDO
F_SEL1
Unused
Input
Input
Input
Input
Input
Power
Power
No connect.
Selects between the crystal or TEST_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs.
LVCMOS/LVTTL interface levels.
Pulldown Single-ended LVCMOS/LVTTL clock input.
Pullup
Pulldown
Pulldown
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded M,
N, and T values. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
clock frequency/N output divider. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Input
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
Power
Output
Power
Input
Pullup
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedence.
Output supply pin.
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C_IN
Input Capacitance
C
Power Dissipation Capacitance
PD
R_PULLUP
R_PULLDOWN
R_OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V_DD, V_DDA, V_DDO = 3.465V
V_DD, V_DDA = 3.465V, V_DDO = 2.625V
Minimum
Typical
4
TBD
TBD
51
51
15
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
8400042AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JANUARY 3, 2006