ICS952906A Datasheet, PDF (3/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952906A
General Description
ICS952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such
as the 93788, it provides all the necessary clock signals for such a system.
The ICS952906A is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1
XTAL
X2
CPU_STOP#
PCI_STOP#
FS (4:0)
SCLK
Sel24_48#
SDATA
MODE
VTTPWRGD#/PD#
Control
Logic
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz
24_48MHz
REF (1:0)
CPUCLKT (1:0)/ITP
CPUCLKC (1:0)/ITP
25MHz (1:0)
3V66 (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
RESET#
I REF
Power Groups
Pin Number
VDD
3
GND
6
10, 17
11, 18
24
23
27
28
34
37
40
43
48
47
Description
REF, Xtal
PCICLK outputs
48MHz Fix, Fix Digital, Fix analog
3V66 outputs
2.5V for 25MHz outputs
CPU outputs
CPU Analog, CPU digital
1236A—08/06/07
3