ICS952906A Datasheet, PDF (11/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952906A
I²C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Control
Type
0
1
Function
Bit 7
-
RID3
R
-
-
Bit 6
-
RID2
REVISION ID
R
-
-
Bit 5
-
RID1
R
-
-
Bit 4
-
RID0
R
-
-
Bit 3
-
VID3
R
-
-
Bit 2
-
VID2
VENDOR ID
R
-
-
Bit 1
-
VID1
R
-
-
Bit 0
-
VID0
R
-
-
I²C Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control
Function
Byte Count
Programming b(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
I²C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
WD Timer Bit 7
WD Timer Bit 6
WD Timer Bit 5
WD Timer Bit 4
WD Timer Bit 3
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
M/NEN
WDEN
WDFSEN
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Control
Function
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
Watch Dog Safe Freq
Programming bits
Type
RW
R
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Latched FS/Byte0
1
Enable
Enable
WD B10 b(4:0)
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
PWD
X
X
X
X
0
0
0
1
PWD
0
0
0
0
1
1
1
1
PWD
0
0
0
0
1
0
1
1
PWD
0
0
0
0
0
0
0
0
1236A—08/06/07
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