ICS950208 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950208
Pin Description (Continued)
PIN PIN
# NAME
PIN
TYPE
DESCRIPTION
25 SDATA
I/O Data pin for I2C circuitry 5V tolerant
26 SCLK
IN Clock pin of I2C circuitry 5V tolerant
27 3V66_3
OUT 3.3V 66.66MHz clock output
28 3V66_2
OUT 3.3V 66.66MHz clock output
29 GND
PWR Ground pin.
30 3V66_1
OUT 3.3V 66.66MHz clock output
31 3V66_0
OUT 3.3V 66.66MHz clock output
32 VDD3V66
PWR Power pin for the 3V66 clocks.
33 GND
PWR Ground pin.
34 AVDD
PWR 3.3V Analog Power pin for Core PLL
This pin establishes the reference current for the differential current-mode output pairs. This
35 IREF
OUT pin requires a fixed precision resistor tied to ground in order to establish the appropriate
36 GNDCPU
current. 475 ohms is the standard value.
PWR Ground pin for the CPU outputs
37 CPUCLKC1
38 CPUCLKT1
OUT ^{"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.}
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
OUT _{resistors are required for voltage bias.}
39 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
40 CPUCLKC0
41 CPUCLKT0
OUT ^{"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.}
External resistors are required for voltage bias.
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Asynchronous active low input pin used to power down the device into a low power state. The
42 PD#
IN internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
43 GNDCPU
power down will not be greater than 1.8ms.
PWR Ground pin for the CPU outputs
44 CPUCLKC2
45 CPUCLKT2
OUT ^{"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.}
External resistors are required for voltage bias.
OUT ^{"True" clocks of differential pair CPU outputs. These are current mode outputs. External}
resistors are required for voltage bias.
46 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
47 GNDREF
PWR Ground pin for the REF outputs.
48 REF0/MULTSEL0*
I/O ^{3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference}
clock.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0464B—08/04/03
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