ICS950208 Datasheet, PDF (10/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950208
Byte 13: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
The Spread Spectrum (12:0) bit will program the spread
precentage. Spread precent needs to be calculated based on the
VCO frequency, spreading profile, spreading amount and spread
frequency. It is recommended to use ICS software for spread
programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUDIV3
CPUDIV2
CPUDIV1
CPUDIV0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
X
X
X
X
X
X
X
X
Description
CPU2 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU(1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
PWD
X
X
X
X
X
X
X
X
Description
3V66(3:2) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
3V66(1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
0464B—08/04/03
10