ICS950208 Datasheet, PDF (11/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
3V66(3:2)_INV
3V66(1:0)_INV
CPU_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
X
X
X
X
X
X
X
X
Description
3V66(3:2) Phase Inversion bit
3V66(1:0) Phase Inversion bit
CPUCLK_2 Phase Inversion bit
CPUCLK Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Div (3:2)
00 01 10 11
Div (1:0)
00
/2
/4
/8 /16
01
/3
/6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/4
/8 /16 /32
01
/3
/6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
ICS950208
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPU_Skew 1
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
CPU_Skew 0
Reserved
Reserved
PWD
0
1
0
0
0
1
0
0
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
These 4bits control
CPU-3V66(3:2)
These 4 bits control
CPU-3V66(1:0)
PWD
0
1
0
0
0
1
0
0
Programming Sequence
0 0 0 0 0ps Reserved
0 1 0 0 150ps Reserved
1 0 0 0 300ps Reserved
1 1 0 0 450ps Reserved
1 1 0 1 600ps Reserved
1 1 1 0 750ps Reserved
1 1 1 1 900ps Reserved
Reserved
Reserved
0464B—08/04/03
11