ICS8430-111 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-111
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32
4
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
Type
Description
Input
Input
Pulldown _{M divider inputs. Data latched on LOW-to-HIGH transition}
of nP_LOAD input. LVCMOS/LVTTL interface levels.
Pullup
5, 6
N0, N1
Input Pulldown _{Determines output divider value as defined in Table 3C}
7
N2
Input
Pullup ^{Function Table. LVCMOS/LVTTL interface levels.}
8, 16
9
10
11, 12
13
14, 15
17
18
19
20
21
22
23
V_EE
TEST
V_CC
FOUT1,
nFOUT1
V_CCO
FOUT0,
nFOUT0
MR
S_CLOCK
S_DATA
S_LOAD
V_CCA
CLK_SEL
TEST_CLK
Power
Output
Power
Output
Power
Output
Input
Input
Input
Input
Power
Input
Input
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between differential clock or test inputs as the PLL reference
source. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK
when LOW. LVCMOS/LVTTL interface levels.
Test clock input. LVCMOS/LVTTL interface levels.
24
CLK
Input Pulldown Non-inverting differential clock input.
25
nCLK
Input
Pullup Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS/LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
51
51
Maximum
4
Units
pF
kΩ
kΩ
8430DY-111
www.icst.com/products/hiperclocks.html
3
REV. F JUNE 1, 2005