ICS8430-111 Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-111
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
CC
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8430DY-111
www.icst.com/products/hiperclocks.html
10
REV. F JUNE 1, 2005