ICS8430-111 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-111
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency. The VCO of the PLL operates over
a range of 200 to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is initially LOW. The data on
inputs M0 through M8 and N0 through N2 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in
the parallel input mode. The relationship between the VCO fre-
quency, the input frequency and the M divider is defined as
follows: fVCO = f_IN x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 100 ≤ M ≤ 350. The frequency
out
is
defined
as
follows:
fOUT
=
fVCO
N
=
f_IN
x
M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK.The serial mode can
be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
T1 T0
00
01
10
11
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
tt
SH
nP_LOAD
M0:M8, N0:N1
M, N
PARALLEL LOADING
nP_LOAD
tt
SH
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8430DY-111
www.icst.com/products/hiperclocks.html
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REV. F JUNE 1, 2005