ICS9248-92 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – Mobile Pentium IITM System Clock Chip

Pin Descriptions
PIN NUMBER
45, 1, 2
3, 10, 17, 24,
31, 37, 43
4
5
6
7, 15
8
9, 11, 12, 13, 14, 16
18
19
20
21
22
23
25
26
27
28, 34
40
42, 41
36, 35, 33, 32, 30, 29
38
39
44
48, 46
PIN NAME
REF [2:0]
GND
X1
X2
MODE
VDDPCI
PCICLK_F
PCICLK [0:5]
SEL100/66#
SDATA
SCLK
VDD48
48/24MHzA
48/24MHzB
VDDCOR
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
VDDSDR
VDDLCPU
CPUCLK [0:1]
SDRAM [0:5]
FB
BUF_IN
PWR_DWN#
VDDREF
ICS9248-92
TYPE
OUT
PWR
IN
OUT
IN
PWR
OUT
OUT
IN
IN
IN
PWR
OUT
OUT
PWR
OUT
IN
OUT
IN
PWR
PWR
OUT
OUT
OUT
IN
IN
PWR
DESCRIPTION
Reference clock Output
Ground (common)
Crystal or reference input, has internal crystal load cap
Crystal output, has internal load cap and feedback
resistor to X1
Input function selection (see table page 3)
Supply for PCICLK_F, PCICLK [0:5], nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
Selects 66.6MHz or 100MHz for SDRAM and CPU
(see tables page 1, 3)
I²C data input
I²C clock input
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHz driver output for USB or Super I/O
Supply for PLL core, nominal 3.3V
SDRAM clock output, fanout buffer output from BUF_IN pin
Halts PCI Bus [0:5] at logic "0" level when low
SDRAM clock output, fanout buffer output from BUF_IN pin
Halts CPU clocks at logic "0" level when low
Supply for SDRAM [0:5], SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
Supply for CPUCLK [0:1] 2.5V nominal
CPUCLK clock output, powered by VDDL2
SDRAM clock outputs, fanout buffer outputs from
BUF_IN pin
Feedback out
Input for SDRAM buffers
When driven active (low) powers down the device into low
power state. Internal clocks are disabled, VCO and crystal
OSC are stopped.
Supply for REF [0:2], X1, X2, nominal 3.3V
Power Groups
VDDCOR = Supply for PLL core
VDDREF = REF [0:2], X1, X2
VDDPCI = PCICLK_F, PCICLK [0:5]
VDDSDR = SDRAM [0:7]
VDD48 = 48/24MHzA, 48/24MHz
VDDLCPU = CPUCLK [0:1]
2