IS61S6432 Datasheet, PDF (9/20 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

IS61S6432
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued)
Symbol
Parameter
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max Unit
tKC
Cycle Time
10 — 12 — 13 — 15 —
ns
tKH
Clock High Time
3.5 — 4 — 6 — 6 —
ns
tKL
Clock Low Time
3.5 — 4 — 6 — 6 —
ns
tKQ
tKQX⁽¹⁾
tKQLZ^(1,2)
tKQHZ^(1,2)
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
—5 —6 —7—8
ns
1.5 — 1.5 — 2 — 2 —
ns
0— 0— 0—0—
ns
1.5 6 1.5 6 2 6 2 6
ns
tOEQ
tOEQX⁽¹⁾
tOELZ^(1,2)
tOEHZ^(1,2)
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
—5 —6 —6—6
ns
0— 0— 0—0—
ns
0— 0— 0—0—
ns
—4 —5 —6—6
ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tSS
Address Status Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tWS
Write Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tAVS
Address Advance Setup Time
2.5 — 2.5 — 2.5 — 2.5 —
ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tAVH
Address Advance Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCFG⁽³⁾
Configuration Setup
35 — 45 — 66.7 — 80 —
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.
Integrated Circuit Solution Inc.
9
SSE003-0B