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IS61S6432 Datasheet, PDF (16/20 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM | |||
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IS61S6432
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating
Range)
Symbol
Parameter
-200(2)
-166
-133
-117
Min. Max. Min. Max Min. Max. Min. Max. Unit
tKC
Cycle Time
5 â 6 â 7.5 â 8.5 â
ns
tKH
Clock High Time
1.6 â 2.4 â 2.8 â 3 â
ns
tKL
Clock Low Time
1.6 â 2.4 â 2.8 â 3 â
ns
tKQ
tKQX(3)
tKQLZ(3,4)
tKQHZ(3,4)
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
â4 â5 â5â5
ns
1 â 1.5 â 1.5 â 1.5 â
ns
0â 0â 0â0â
ns
1 3.5 1.5 5 1.5 5 1.5 6
ns
tOEQ
Output Enable to Output Valid
â 3.5 â 5 â 5 â 5
ns
tOEQX(3)
Output Disable to Output Invalid
0â 0â 0â0â
ns
tOELZ(3,4)
Output Enable to Output Low-Z
0â 0â 0â0â
ns
tOEHZ(3,4)
Output Disable to Output High-Z
â3 â3 â3â4
ns
tAS
Address Setup Time
2 â 2.5 â 2.5 â 2.5 â
ns
tSS
Address Status Setup Time
2 â 2.5 â 2.5 â 2.5 â
ns
tCES
Chip Enable Setup Time
2 â 2.5 â 2.5 â 2.5 â
ns
tAH
Address Hold Time
2 â 2.5 â 2.5 â 2.5 â
ns
tSH
Address Status Hold Time
2 â 2.5 â 2.5 â 2.5 â
ns
tCEH
tZZS(5)
Chip Enable Hold Time
ZZ Standby
2 â 2.5 â 2.5 â 2.5 â
ns
â 8 2 â 2 â 2 â cyc
tZZREC(6)
ZZ Recovery
8 â 2 â 2 â 2 â cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. ADVANCE INFORMATION ONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
16
Integrated Circuit Solution Inc.
SSE003-0B
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