IC41SV4105 Datasheet, PDF (6/17 Pages) Integrated Circuit Solution Inc – 1Mx4 bit Dynamic RAM with Fast Page Mode

IC41SV4105
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
Output High Voltage Level
Test Condition
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
IOH = −2.0 mA
Speed Min. Max. Unit
−5
5
µA
−5
5
µA
1.6
−
V
VOL
Output Low Voltage Level
IOL = 2 mA
−
0.8
V
ICC1
Standby Current: TTL
RAS, CAS ≥ VIH
−
1 mA
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC − 0.2V
0.5 mA
ICC3
Operating Current:
RAS, CAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4
Operating Current:
RAS = VIL, CAS ≥ VIH
Fast Page Mode^(2,3,4)
tRC = tRC (min.)
Average Power Supply Current
ICC5
Refresh Current:
RAS-Only^(2,3)
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
Average Power Supply Current
ICC6
Refresh Current:
RAS, CAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50
−
-70
−
-100 −
-50
−
-70
−
-100 −
-50
−
-70
−
-100 −
-50
−
-70
−
-100 −
70 mA
60
50
55 mA
45
35
70 mA
60
50
70 mA
60
50
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001