IC42S16400A Datasheet, PDF (3/67 Pages) Integrated Circuit Solution Inc – 1M x 16Bit x 4 Banks (64-MBIT) SDRAM

IC42S16400A
60-BALL VF-BGA ( 64M SDRAM )
7
VDD A1 A10 BA0 CS CAS WE NC DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VDD
6
A3
A2
A0 _BA1 NC RAS LDQM VDD NC
VSSQ VDDQ DQ4 VSSQ VDDQ DQ0
5
4
3
2
A4
A5
A7
A9 NC CLK UDQM NC
NC VDDQ VSSQ DQ11 VDDQ VSSQ DQ15
1
VSS A6
A8 A11 CKE NC NC
NC DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 VSS
RPNML KJ HG FE DCBA
PIN DESCRIPTIONS
A0 - A11
BA0,BA1
DQ0 - DQ15
CLK
CKE
CS
RAS
CAS
WE
LDQM,UDQM
VDD/VSS
VDDQ/VSSQ
NC
Address
Bank Address
Data Input/Output
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
Row Address : RA0 - RA11, Column Address : CA0 - CA7
Auto-precharge flag : A10
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Multiplexed data input / output pin
The system clock input.All other inputs are registered to the SDRAM
on the rising edge of CLK
Controls internal clock signal and when deactivated,the SDRAM will
be one of the states among power down,suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
RAS,CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Power supply for internal circuits and input buffers
Power supply for output buffers
No Connection
Integrated Circuit Solution Inc.
3
DR039-0A 02/19/2004