IC42S16400A Datasheet, PDF (2/67 Pages) Integrated Circuit Solution Inc – 1M x 16Bit x 4 Banks (64-MBIT) SDRAM

IC42S16400A
1M x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Single 3.3V (± 0.3V) power supply
• High speed clock cycle time -6: 166MHz,
-7: 133MHz<3-3-3>
• Fully synchronous operation referenced to clock
rising edge
• Possible to assert random column access in
every cycle
• Quad internal banks contorlled by A12 & A13
(Bank Select)
• Byte control by LDQM and UDQM for
IC42S16400A
• Programmable Wrap sequence (Sequential /
Interleave)
• Programmable burst length (1, 2, 4, 8 and full
page)
• Programmable CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge
command
• Package 400mil 54-pin TSOP-2 and 60ball(64M)
VF-BGA
• Pb(lead)-free package is available
DESCRIPTION
The IC42S16400A are high-speed 67,108,864-bit syn-
chronous dynamic random-access memories, orga-
nized as 1,048,576 x 16 x 4 (word x bit x bank),
respectively.
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture and clock
frequency up to 166MHz for -6. All input and outputs are
synchronized with the positive edge of the clock.The
synchronous DRAMs are compatible with Low Voltage
TTL (LVTTL).These products are packaged in 54-pin
TSOP-2 and 60ball(64M) VF-BGA.
PIN CONFIGURATIONS
54-Pin TSOP-2
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
VDD 14
LDQM 15
WE 16
CAS 17
RAS 18
CS 19
BA0 20
BA1 21
A10 22
A0 23
A1 24
A2 25
A3 26
VDD 27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR039-0A 02/19/2004